Host Programming

22 Mar

Host Programming
To communicate with a MultiMediaCard, the host uses the MultiMediaCard protocol to send commands, receive responses, and send and receive additional data as required by commands. On a lower level, the commands, responses, and data each consist of one or more bytes. This chapter explains how the individual bytes travel on the SPI bus. Chapter 5 describes the protocol for sending MultiMediaCard commands.

SPI is a synchronous bus, where the host provides a clock signal that determines when the host and MultiMediaCard read and write data. The interface provides options for configuring the clock polarity and the phase, or timing, relationship between the clock and data bits. The clock polarity determines whether the clock is high or low when idle. The clock phase determines whether input data is valid on the rising or falling clock edge. For MultimediaCards, the clock line must be high when idle and data is valid on the rising clock edge.

SPI hosts are generally more flexible than SPI devices. Microcontrollers with SPI support typically provide configuration registers for selecting a clock polarity and phase to match a device’s requirements.

Figure 4-2 and Table 4-3 show the timing requirements for MultiMediaCards. The cards latch data received on the DataIn line on SCLK’s rising edge. The data must be valid 3 nanoseconds before and after the rising edge. When sending data on DataOut, the data is valid at least 5 nanoseconds before and after SCLK’s rising edge. In practice, MultiMediaCards typically latch output data on SCLK’s falling edge, so the data is valid for a longer period.

Data on the bus travels most significant bit first. Transmitting a byte requires eight clock cycles. The host must generate clock cycles when trans-

Table 4-3: Timing requirements for MultiMediaCards on a bus with 10 or fewer cards.

Figure 4-2: A MultiMediaCard data reads data on SCLK’s rising edge and writes data that the MultiMediaCard host can read on SCLK’s rising edge.

mitting bytes on DataIn, when receiving bytes on DataOut, and at other times as required by the MultiMediaCard specification.

Hardware Ports
The PIC18F4550 and other microcontrollers with hardware support for SPI hosts contain these components:

• Three port pins to provide the SCLK output, DataOut input, and DataIn output.
• One or more generic port pins to provide a firmware-controlled CS output for each device. If a host has many devices to control, a host can use an external decoder chip such as a 74HC138 to control the CS lines.
• One or more buffers to hold data waiting to transmit and received data.
• A clock source to drive the SCLK output.
• A shift register to clock data out on the DataIn line and clock data in on the DataOut line.
• Configuration registers to enable setting clock polarity and phase, setting the clock’s frequency, and enabling the SPI port.

Many microcontrollers with SPI support also enable configuring the microcontroller as either a host (master) or device (slave). For MultiMediaCard communications, the microcontroller must be a host.

When the PIC18F4550’s SPI port has been configured as a host, device firmware can send and receive data by bringing CS low and writing to the SPI buffer. Writing to the buffer causes SCLK to generate 8 clock cycles, latching a bit from the buffer onto DataIn on each cycle.

Each write operation also reads a byte from the DataOut line into the buffer. If there is no data to receive, firmware can ignore the received byte. To read a byte when there is no data to send, firmware can write a byte that holds the line in the idle state (FFh for MultiMediaCard communications). When eight bits have been transferred, the port hardware copies the byte read on DataOut from the shift register to the buffer, where firmware can access the value.

Firmware-controlled Ports
A microcontroller that doesn’t have hardware SPI support can control all of the communications in firmware. In addition to toggling CS to select and deselect a card, the firmware must bring SCLK high and low as needed, write each bit to transmit at the appropriate time on DataIn, and read each received bit at the appropriate time on DataOut.

The MultiMediaCard SPI bus has no minimum required clock frequency or duty cycle except that the clock’s high and low pulses must be at least 10 nanoseconds wide. Firmware can toggle SCLK as needed without having to worry about maintaining a frequency or duty cycle. The maximum SCLK frequency is 20 Mhz, and the maximum rise and fall times are 10 nanoseconds. (For buses with more than 10 MultiMediaCards, the maximum SCLK frequency is 5 Mhz and the maximum rise and fall times are 50 nanoseconds.)

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