The I2C Bus

10 May

The I2C Bus: Philips developed the I2C (Inter-IC) bus in the early 1980s for mass-produced items such as televisions and audio equipment. The I2C bus is a bidirectional, two-wire serial bus that provides a communication link between multiple integrated circuits (ICs) in a system. I2C has become a generally accepted industry standard for embedded applications and has been adopted by many IC manufacturers. All devices that are compatible with the I2C bus include an on-chip interface that allows them to communicate directly with each other on the bus. The I2C bus supports three data transfer speeds: standard, fast-mode, and high-speed mode. All data transfer speeds modes are backward compatible. Each device on the I2C bus has a unique address and can operate as either a transmitter or receiver depending on its function.

What Is the I2C bus?

I2C, or Inter Integrated Circuit, is a bus protocol developed by Philips Semiconductor for communication between integrated circuits. A document describing the complete bus protocol standard is freely available for download from the Philips website1, but the protocol itself is patented and the integrated circuits that make use of it are subject to a sort of licensing agreement with Philips. I2C is primarily used in embedded applications where a microcontroller communicates with and controls a variety of peripheral devices. Digital potentiometers, EEPROMS, A/D converters, phase-locked loop synthesizers, microcontrollers and audio/video products are all good examples of products that use I2C. Some of the most salient features of the bus are found in the following list:

• The I2C bus consists of two signals: the serial clock (SCL) and a serial data line (SDA).

• The bus is bidirectional and makes use of pull-up resistors. I2C devices either pull the bus to logic low, or allow the bus pull-up to pull it high.

• The bus has three speed modes, a standard mode (<100 kHz), a fast mode (100 kHz – 400 kHz) and a high-speed mode (400 kHz – 3.4 MHz).

• Data transfer is based on 8-bit words.

• Every device on the bus has a unique address, which is either 7 bits or 10 bits wide.

• The bus is based on a master/slave device relationship. Devices can be one or the other or switch back and forth. The bus can have more than one master and features a process called “arbitration” to resolve conflicts when multiple devices try to control the bus at once.

• The number of devices on the I2C bus is limited by the capacitance of the bus, which must be less than 400 pF.

The I2C Bus in More Detail
We’ve outlined the general characteristics of the I2C bus, so let’s take a look at how it all works in more detail.

The master/slave concept in I2C
In the Dallas Semiconductor 1-Wire bus protocol, there can be only one master on the bus, and every other device is a slave. In I2C, things are more complicated. Devices can be masters sometimes, slaves sometimes, and sometimes there can be multiple masters trying to control the bus at the same time. The best way to delve into this is to introduce some basic terminology from the I2C specification. It is important to note that these definitions relate to the I2C bus, and if we use the same words in the context of discussing a different bus protocol, they have slightly different meanings.

The most interesting feature is the multimaster concept in which several I2C devices may try to be a master at the same time. The I2C protocol handles this through “synchroniza- tion” and “arbitration.” Synchronization is the process by which masters all use the same clock. It relies on the fact that the clock line (SCL) is pulled high by a pull-up resistor. The result is that the SCL line value is the wired-AND of all the SCL connections from the various I2C devices on the bus. Masters generate their own clock during data transfers. If two or more masters attempt a data transfer at the same time, they will all attempt to put their own clock on the SCL line. Each “would-be” master generating a clock is going to try to pull the clock line low for a period of time (the low period) and then let the bus be pulled high for a period of time (the high period). They each have internal timers metering out these periods of time. Different devices may have slightly different times for the low periods and high periods. The first clock to go from high to low “resets” the clock- generating circuitry of all the other “would-be” masters and starts them all counting out their low period. The device with the longest period will still be holding the SCL line low when all the other devices have released it to go high. That device will determine the low period of the SCL line.

When the last device releases the SCL line and it goes from low to high, all the devices now start counting out their high period. The first device to pull the SCL line from high to low causes the entire process to be repeated. The resulting waveform on the SCL line is what is called the synchronized clock. It has a low period equal to the longest low period of all the “would-be” masters and a high period equal to the shortest high period of all the “would-be” masters.

The process of arbitration is very similar. The synchronization process has not determined which device is the master—it has only determined which device has defined a clock they can all agree upon. The SDA (serial data) line is also a wired- AND, this time of all the individual SDA values. As each would-be master is participating in generating the clock, it is also putting data (in the form of individual bits) on the SDA line. If one device puts out a logic 1 while another device outputs a logic 0, the logic 1 is eliminated by the wired AND. Any device whose bit is eliminated by a wired AND loses the arbitration and will not become the master during this data transfer. So the last device to put out a logic 1 on the SDA line wins the arbitration and takes command of the bus, which means it completes the data transfer that’s already been started.

The I2C data format
There are a number of different elements that make up the bit format on the I2C bus.
These are:
• The start condition
• The address
• The read/write bit
• The acknowledge or not acknowledge bit
• The data
• The stop condition

The start condition
The start condition indicates the beginning of communication by a master. It occurs when the master pulls the data line (SDA) from high to low while the clock is high. The start condition always comes from the master.

The address
The address consists of a series of bits (7 bits in the examples we’ll discuss) and each bit must be valid before the rising edge of the clock and be held valid until after the falling edge of the clock. The address bits always come from the master.

The read/write bit
The read/write bit occurs immediately after the address bits. Like the address bits, it must be valid before the clock goes high and held valid until the clock goes low. The read/write bit always comes from the master.

Table 11-2: Table showing meaning of the read/write bit

The acknowledge bit
The acknowledge bit is used by both the master and slave to indicate continued responses to communication. Like the address and R/W bits, it must “overlap” the clock. Its exact use will be illustrated in more detail when we take a detailed look at the communications between master and slave. Both the master and slaves can produce an acknowledge bit.

Data bits
Data occurs in 8-bit chunks and after each chunk an acknowledge bit is issued. Data must overlap clock in the same fashion as the address, R/W and acknowledge bits.

The stop condition
The stop condition ends the communication and indicates that the bus is free. To generate a stop condition, the master lets the bus be pulled high while the clock is high. The stop condition is always generated by the master.

Figure 11-1: Diagram showing start, stop, and data with respect to clock

The data format for basic I2C communication using 7-bit addressing comes in three very similar configurations, corresponding to three possible actions:

•  Master writing to slave. The process of the bus master writing to a receiving
slave device proceeds as follows:
a) The master issues a start condition.
b) The master writes the 7-bit address to the bus.
c) The master issues 1-bit R/W indicator (0 for write).
d) The slave issues an acknowledge bit (logic 1).
e) The master issues 8-bit data chunks, each followed by a 1-bit acknowledge from the slave.
f) This continues until the master issues a stop condition.

•  Master reading from  slave. The process of the bus master reading from the
slave proceeds much like that of writing to the slave.
a) The master issues a start condition.
b) The master writes the 7-bit address to the bus.
c) The master issues a read/write bit (1 for read).

Figure 11-3: I2C Read
d) The slave issues an acknowledge bit (logic 1).
e) The slave outputs 8-bit data chunks, each of which is acknowledged by
the master with an acknowledge bit (logic 1).
f) When the master is done reading, it will output a “not acknowledge” (logic 0).
g) Followed by the stop condition.

• Master doing one, then doing the other. When the master both reads from and writes to a slave, the result is what is referred to as the combined format. Like the name implies, it’s basically a combination of the two previous examples. If we were to first write, then read, our process would be:

a) Master issues a start condition.
b) Master writes the 7-bit address, followed by a read/write bit (0 for write).
c) The slave issues an acknowledge bit (logic 1).
d) Master writes 8-bit chunks, and after each chunk, the slave issues an acknowledge bit (logic 1).
e) When the master is done writing, and now wants to read, it reissues the start condition, reissues the address, and asserts the read bit (logic 1).
f) The slave will respond with an acknowledge bit (logic 1) followed by 8- bit data chunks. After each 8 bits of data, the master will issue an acknowledge bit (logic 1). When the master is done reading, it will issue a “not acknowledge” (logic 0) and a stop condition.

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