The processor and oscillator module
The CPU on TINI, the DS80C390, is technically called a Dual CAN high-speed microprocessor. It’s compatible with the 8051 instruction set. It has six 8-bit ports. Under software control, most have one or more functions. The DS80C390 has two integrated CAN controllers, and it has an integrated UART, capable of controlling two serial ports. This processor is extremely flexible and there are a number of ways it can be used. We will concern ourselves with how it is used on the TINI stick. We’ll start by looking at its pin-out and examining what all of its signals do for us. Figure 6-3 shows a close up of the CPU on the TINI schematic. Notice that there are numerous labels for each pin. Let’s make some sense of this, by taking a closer look at a couple of the pins.
Referring to the figure, the label P0 refers to port 0 of the CPU’s six 8-bit ports. P0.0 is the least significant bit in that port, P0.1 the next bit, etc. The label AD0 accompanying the P0.0 label is an indication of that pin’s function as described in the general DS80C390 data sheet (AD0 indicates that it is an 8-bit bus that can be either an address or data bus, and it is the least significant bit). The label 55 is the pin number on the package, and the label D0 is the net name assigned to this pin on the TINI schematic. It’s an indication of how this pin is being used by TINI. Unless otherwise noted, we will make use of the port/bit designator (P0.0), and the TINI schematic net name. Let’s go around the CPU and examine what all these signals do. Port0, P0.0 to P0.7, is the data bus and consists of TINI signals D0 to D7. Port1, P1.0 to P1.7, is part of the address bus and makes up TINI signals A0 to A7. Port2, P2.0 to P2.7, is more of the address bus and makes up TINI signals A8 to A15. Port3, P3.0 to P3.7, provides a variety of different functions:
• P3.0 is the RX signal, the receive input for the CPU’s serial port.
• P3.1 is the TX signal, the transmit output for the CPU’s serial port.
• P3.2 is the /SMCINT signal. This is an interrupt input, coming from the Ethernet controller device.
• P3.3 is the /EXTINT signal. This is an interrupt input, coming from a user- defined external hardware source. A simple demo program describing how to use this hardware interrupt is included in Chapter 9 (ExtIntDemo.java).
• P3.4 is the SMCRST signal. This is an output that serves to reset the Ethernet controller. The SMCRST signal is used to disable the outputs of various peripherals during power-up. This signal starts out high and goes low only after TINI has completed its reset sequence and the firmware is ready to put the peripheral drivers into a known state (like the network IC and parallel I/O). Because this signal goes low only after the TINI firmware is up and running, it is a good signal to use to prevent I/O activity during start-up.
• P3.5 is the INTOWB signal. This is the internal 1-Wire bus and is bi-direc- tional.
• P3.6 is the /WR signal. This is the active low write enable for memories and is associated with the data and address buses.
• P3.7 is the /RD signal. This is the active low read enable for the memories and is also associated with the data and address buses. Port 4, P4.0 to P4.7, provides the remaining address signals and chip enable signals:
• P4.0 is the /CE0 signal. This is the chip enable output for the flash memory. It’s routed off stick and doesn’t actually go to the on-board flash. The on- board flash, U2, has a signal named /RCE0 as its chip enable, instead. /RCE0 comes from the TINI edge card connector. For many applications, such as when using an E20 socket board or the Vinculum proto-board, you are prob- ably going to route the /CE0 output on the SIMM edge connector right back into the /RCE0 input signal on the SIMM. The reason they didn’t just hardwire the /CE0 signal from the CPU directly to the flash memory has to do with flexibility. By not hardwiring it, we can use the /CE0 externally to select a different, external flash, should we desire it.
• P4.1 is the /CE1 signal. This is the chip enable output for U4, the 512k static ram, which is SRAM0. It doesn’t go directly to SRAM0, but is gated through U13. The U13 device is effectively an or gate controlled by U10, the RAM nonvolatizer. /CE1 does not go off stick.
• P4.2 is the /CE2 signal. This is the chip enable output for U5, the second 512k static ram, which is SRAM1. Depending on the stick version you have, this component is most likely not installed. Like /CE1, this signal is not routed directly to the ram, but rather, it is gated through the or gate U13, which is controlled by the ram nonvolatizer U10. /CE2 is also not routed off stick.
• P4.3 is the /CE3 signal. This a chip enable output that serves a variety of functions. It serves as the address enable for the Ethernet controller, chip enable for the real-time clock, and it’s routed off stick for use decoding addresses for memory reads and writes to peripheral devices.
• P4.4 to P4.7 are the remaining address bus signals, A16 to A19. Port 5 represents a variety of functions.
• P5.0 is the CTX signal. This is the CAN transmit output signal for the CAN0 CAN controller. It is routed off the stick. This pin is also used for the SCL line for I2C communication.
• P5.1 is the CRX signal. This is the CAN receive input signal for the CAN0 CAN controller. It is routed off the stick. This pin is also used for the SDA line for I2C communication.
• P5.2 is the RX1 signal. This is the input representing the received data from the external 1-Wire bus data coming from the iButton interface circuitry. This signal is not routed off stick. This pin can also be used for either the CTX signal (CAN transmit) for the CAN1 CAN controller or the RX signal for the serial1 port.
• P5.3 is the TX1 signal. This is an output representing the data to be transmit-ted out the external 1-Wire bus via the iButton interface circuitry. This signal is routed off stick. This pin can also be used for either the CRX signal (CAN receive) for the CAN1 CAN controller, or the TX signal for the Serial1 port.
• P5.4 to P5.7 are the /PCE0, /PCE1, /PCE2, and /PCE3 signals. These are peripheral chip enable outputs and can be used as chip enables to perform memory reads and writes to peripheral devices. They are routed off chip.
You have program control of some of these through ports (port 3 and port 5) using the BitPort class of the TINI API. You can access Port5 through the BytePort class as well. Refer to the TINI API documentation for more information on these classes. Beyond the six 8-bit ports, there are a handful of additional CPU signals that are used by TINI. We’ll refer to them by the net name on the TINI schematic. CPURST is the CPU reset input.
When this signal is pulled high, the CPU resets. This signal comes from a small circuit that converts the DTR signal into the CPURST signal. CPURST is routed off stick. It can be used by off-stick devices that need to reset the CPU, or, as a way to reset off-stick devices, when the CPU resets. /RSTOL is the reset output low signal. It is an active low output signal that goes low whenever the CPU is resetting, the watchdog timer has expired, during the crystal warm-up phase, or whenever the CPU VCC drops below the value on CPURST. /RSTOL controls the reset on the real time clock, U7. It is not routed off-stick.
XTAL1 and XTAL2 are the crystal inputs the CPU. /PSEN is the program store enable output signal. This is an active low CPU output that is low whenever the CPU is accessing memory. It acts as an output enable for the flash ROM (U2), SRAM0 and SRAM1 (U4 and U5), the real-time clock (U7), and the Ethernet controller (U3).