The TINI Hardware

7 May

The TINI Hardware

This chapter examines the TINI hardware and some of the associated interface boards that allow you to connect to it. We will begin by systematically reviewing each component on the TINI schematic. We will also present useful programs that demonstrate some of the features of the TINI API as they relate to the hardware and provide tables and charts that will be used in the remainder of this book.

What is TINI?
The term TINI can actually refer to more than one thing. With respect to hardware, TINI is a design concept that consists of an embeddable chipset that you can incorporate into your own products to make them Java-powered and web-enabled. That chipset consists of a DS80C390 microprocessor, a flash ROM, and a static RAM. The term TINI can also be applied to the “TINI stick,” which is a specific, pre- manufactured design implementation using the TINI chipset. The “stick” consists of the TINI chip set, along with a host of interface devices mounted on a 72-pin SIMM. It runs on 5V DC, (+/- 5%, 250mA) and utilizes an 18.432-MHz clock, which is frequency doubled to 36.864 MHz after the initial portions of the booting process. Dallas Semiconductor has created this as a reference design to give people an easy way to get up to speed using the TINI chipset. You can use the TINI stick in your products, by simply embedding it as is. Alternatively, you can use it as a debugging platform to develop your design, then later build the chip set into your application. When we discuss TINI in this chapter, we will be referring to the pre-made reference design, the “TINI stick.”

Versions

There have already been a variety of different versions of the TINI stick. The original design used a 68-pin SIMM instead of the 72-pin SIMM used now. Current versions now come with a choice of either 512k or 1Mb of RAM. Unless otherwise noted, we will be discussing the 512k version of the device as shown in schematic version D, dated Oct 12, 2000 (both memory versions are the same design and board—the 512Mb version simply has half the memory).

A high-level look at TINI
Included with this book is the complete schematic for the TINI stick. Before we delve into it in detail, let’s take a high-level look at the design of the TINI stick1.

What’s in a TINI stick?
• A Dallas Semiconductor microcontroller, the DS80C390, which is a descen- dent of the 8051. It has six 8-bit ports that can be used for a variety of functions (more on that later).

•An 18.432-MHz oscillator for the microcontroller.

• A 512k x 8 static RAM, with space on the circuit board for an additional 512K x 8 static RAM. The design uses a 19-bit address space and has separate chip selects for the two RAM devices. This gives TINI a theoretical on-board RAM potential of 2Mb (by using 1Mb x 8 RAMs instead of 512k). The RAM devices are for user program storage.

•A 512k x 8 FLASH ROM. This is divided into 8 banks, and it houses the bootstrap loader, the runtime environment, and the primary Java application (frequently slush).

•A Dallas Semiconductor real-time clock, so that applications have access to true “time.”

•A battery, which provides power to the real-time clock and the static RAM devices when the board isn’t powered up.

•A RAM nonvolatizer subsystem that works with the battery so that user programs remain in the RAMs even when the stick is powered down.

•A DS2480 iButton interface, so that TINI can talk to external 1-Wire devices. There is also an internal 1-Wire bus on the stick, used for communicating with on-board 1-Wire devices.

•An RS232 interface that provides level shifting to the serial interface of the microprocessor.

•A 10-Base-T Ethernet interface.

•Miscellaneous decoupling capacitors, resistors, status LEDs, and jumpers.

The TINI stick has additional capabilities, such as I2C and CAN interfaces, that are an integral feature of the DS80C390 microprocessor.

A quick look at how it works
When TINI is powered up, the CPU first copies the bootstrap loader from the flash memory to a 4k SRAM located inside the CPU itself. Then it transfers control to the runtime environment (tini.tbin), which ultimately will start the primary Java applica- tion. The primary Java application can be the slush operating system (slush.tbin), or some other Java program that has been installed as a .tbin file. The loader, runtime environment, and primary Java application reside in the flash memory. Other applica- tions that are executed later, by the primary Java application, reside in RAM as .tini files. The flash memory is nonvolatile by virtue of its technology. The RAM is made nonvolatile through the use of a battery backup. Additionally, you can change the contents of the flash, by loading in a different .tbin file (such as an updated tini.tbin or slush.tbin) and the contents of the RAM will remain unchanged. The boot process on TINI occurs as the result of a reset and there are a couple of different ways the reset can occur. First, it can reset as the result of the power being turned off and on. This is called a power-on reset (POR). Second, the TINI CPU can be reset with the power already on, by having its CPURST line pulled high. This is referred to as an external reset. External resets and PORs behave somewhat differ- ently. During a POR, the bootstrap loader is loaded into the CPU and then immediately allows the runtime environment to take over. During external resets, the device reboots, but during the booting process the bootstrap loader will wait to receive a special pattern of characters before turning control over to the runtime environment. If it receives this pattern of characters within three seconds of the reset, the loader will execute a mini command shell that can be controlled via the serial0 port. That shell can be used to load new software into the flash. If the loader doesn’t see this pattern within 3 seconds, it will continue the normal booting process, and transfer control to the runtime environment and primary application2. This is how the bootstrap loader gets its name—it is the bit of firmware we use to load a new runtime environment or a new primary Java application into the TINI flash.

The Various Components of the TINI Stick
Having introduced the basic TINI system, let’s take a more detailed look at each of these components.

The SIMM (Single Inline Memory Module) edge connector
The TINI stick connects to the outside world through a 72-pin SIMM edge connector, mechanically identical to the ones used on PC memory modules. To make use of the TINI stick, you must mate with this connector in some fashion. The E10/E20 socket board, or the Vinculum proto-board are two examples of products that mate with the TINI edge connector and provide interfaces to its signals.

1 1-Wire bus with slew-rate-controlled pull-down, active pull-up, ability to switch in Vpp to program EPROM, and ability to switch in Vdd through a low-impedance path to program EEPROM or to perform a temperature conversion. 2 Vpp may be connected to +12V DC to allow EPROM programming with the on-board DS2480. If Vpp is not used in this manner, it must be connected to Vcc. 3 To execute from the on-board Flash ROM, connect CE0 to RCE0. If an external boot-up memory is provided, RCE0 must be pulled high (Vcc) to disable the on-board Flash ROM or data bus interference could occur. Logic in the CE0 to RCE0 path must take care to present minimal delay (< 6 ns) to the CE0 signal. 4 Address bus, data bus and strobe lines are subject to strict loading limitations. Exceeding these limits can cause erratic system operation with on-board as well as off-board resources. Be sure to buffer any signals that will be heavily loaded off-board. Always adhere to the design specifications to assure reliable system operation. 5 Must be pulled high (Vcc) if not used. 6 The internal 1-Wire bus (INTOW) is a micro-controller port pin that drives the CPU status LED and links to the board’s 1-Wire EPROM memory chip that contains the DSTINI1’s Ethernet MAC address. Other 1-Wire devices may be connected to this bus in the future to convey configuration DSTINI1 data to the DSTINI. If this bus is shorted to ground (low) during system boot-up, a Master Clear will be invoked. This forces the contents of the SRAM to be reinitialized. 7 CPURST must be taken high (Vcc) and then released to cause a reset of the DSTINI1. An active state on the DTR232 will also take this line high. This line is pulled down through a 22k Ω pull- down on-board. 8 The RS232 level DTR control line is used to invoke a DSTINI1 reset when asserted. This is to facilitate loaders and diagnostic equipment that must invoke a reset of the board to gain control of the system. This line is pulled to -8 V via 22K ohms and has a 0.01 µF capacitor filter to prevent cross talk on an open DTR conductor from causing spurious resets of the DSTINI if this function is not used. 9 TINI board power consumption is rated at no more than 250 mA.

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