Transferring Data

22 Mar

Transferring Data
The code excerpts that follow show how the PIC18F4550’s SPI port sends and receives data. Some of the information is specific to the chip, but other
microcontrollers with SPI ports use similar architectures to implement SPI ports.

Default States
The host brings a card’s CS line low to select the card. In MultiMediaCard communications, when CS is low and the DataIn output isn’t transmitting, the host must hold DataIn high. When CS is low while the DataOut output isn’t transmitting and the card isn’t busy, the card holds DataOut high. When the clock is idle, the host must hold SCLK high. On completing a command and any responses to it, the host brings the card’s CS line high to deselect the card.

SPI on the PIC18F4550
The PIC18F4550 has a Master Synchronous Serial Port (MSSP) module that can be configured as an SPI or I2C port. The MSSP manages the sending and receiving of data on an SPI or I2C bus. (I2C is another type of syn-chronous serial port used by serial EEPROMs and other peripheral chips.) When using SPI, the port can function as a host or device. Table 4-4 shows the port pins used by the chip’s SPI port.

Registers
The PIC18F4550 has six registers that store information related to SPI communications.

The MSSP Status Register (SSPSTAT) contains status and control information relating to the port. Table 4-5 shows the functions of the SSPSTAT bits.

MSSP Control Register 1 (SSPCON1) contains additional status and control information relating to the port. Table 4-6 shows the functions of the SSPCON1 bits.

The Serial Receive/Transmit Buffer Register (SSPBUF) holds a received byte or a byte waiting to transmit.

The MSSP Shift Register (SSPSR) holds the bits in a byte being received or a byte that is transmitting. Firmware can’t access the SSPSR.

In Peripheral Interrupt Enable Register 1 (PIE1), bit 3 is the master SPI interrupt enable bit. When the bit equals 1, the interrupt is enabled.

In Peripheral Interrupt Request (Flag) Register 1 (PIR1), bit 3 is the master SPI interrupt flag bit. When this bit equals zero, the SPI port is waiting to transmit or receive. When the bit equals 1, a transmit or receive operation is complete. Firmware that uses this interrupt should clear the bit in the interrupt-service routine that services the interrupt.

Microchip’s MPLAB C18 C compiler provides a processor definition module for the PIC18F4550 (p18f4550.asm). The module defines names for the registers. These declarations from the compiler file p18F4550.h enable accessing SSPBUF and the bits in SSPCON1 and SSPSTAT:

extern volatile near unsigned char SSPBUF;
extern volatile near unsigned char SSPCON1;
extern volatile near unsigned char SSPSTAT;

Table 4-4: The PIC18F4550’s built-in SPI port uses three port pins (plus additional pins as needed for CS outputs).

extern volatile near struct {
unsigned SSPM0:1;
unsigned SSPM1:1;
unsigned SSPM2:1;
unsigned SSPM3:1;
unsigned CKP:1;
unsigned SSPEN:1;
unsigned SSPOV:1;
unsigned WCOL:1;
} SSPCON1bits;
extern volatile near struct {
unsigned BF:1;
unsigned UA:1;
unsigned R_W:1;
unsigned S:1;
unsigned P:1;
unsigned D_A:1;
unsigned CKE:1;
unsigned SMP:1;
} SSPSTATbits;


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