Wire Reset Details

9 May

1-Wire Reset Details: A reset halts whatever is taking place on the bus and prepares devices for the beginning of a new communication cycle. A reset begins when the master pulls the bus low for a period greater than 480 µs. There is no upper limit as to how long the bus master can hold the bus low during a reset. The slave devices, upon seeing the bus go low, use their internal clock to time how long the bus is being held low. If the period exceeds 480 µs, they know the master has issued a reset. The slaves wait until the master releases the bus, by letting it be pulled high by the 5K pull-up resistor that needs to be present somewhere on the bus. Upon seeing the bus go high, the slaves then use their internal timer once again to count out a delay that can be anywhere from 15-60 µs, and then they issue a “presence pulse,” by pulling the bus low for a period of time that can be anywhere from 60-240 µs. At the completion of this process, the slave devices know that they have been reset and to await a further command. They now listen to the bus. The master, on the other hand, knows whether or not there are any 1-Wire devices connected to the net by virtue of the presence pulse. The master doesn’t necessarily know what type or how many devices are on the net, but if it sees a presence pulse, it knows there is at least one device. It’s much easier to understand this with a picture.

Figure 10-5: Reset timing diagram and textual flow

1-Wire Data Communication Details
The other type of communication on the 1-Wire bus is data communications, the reading and writing of individual bits. While the process isn’t exactly simple, it can be understood if you go through it carefully and review it a couple of times.

Data transfer on the 1-Wire bus occurs in time slots, which are predetermined windows of time. As we’ve said, communication always begins with an action on the part of the bus master, and consistent with this, time slots begin when the master pulls the bus low. What differentiates this from the reset is that the duration is much shorter. 1-Wire slave devices then keep track of whether or not they should be listening or responding, and the time since the last falling edge on the bus. If the master wants to write a 1 to the bus, it will pull the bus low for a period not to exceed 15 µs and then the master releases the bus so that it can be pulled high by the pull-up resistor for the remainder of the timeslot, which can be between 60 µs and 120 µs wide. If the master wants to write a 0 to the bus, it pulls the bus low and holds it for the entire timeslot, and then releases it, letting it be pulled high. If the bus master is writing to the bus, then the 1-Wire slave devices are reading from the bus. Reading by the 1-Wire slaves devices is accomplished by sampling the bus at a time at least 15 µs after the master pulls the bus low.

Figure 10-6: Master writing one, writing zero, 1-Wire slaves reading

How does the master read from the 1-Wire bus and the 1-Wire slave devices write to the bus? Once again, communication on the 1-Wire bus is initiated by the bus master, who pulls the bus low and holds it low for a period not to exceed 15 µs. The 1-Wire slave devices, who are now writing to the bus, will meter out a 15-µs delay from the time they saw the master pull the bus low, and then place their data on the bus. This means that if they want to write a 1, they allow the bus to be pulled high. If they want to write a 0, they pull the bus low. They hold this value until the end of the timeslot and then release the bus. The bus master waits at least 1 µs and then samples the value from the bus. This is also much easier to understand with a picture.

Figure 10-7: Slaves writing one, writing zero, master reading

This description begs two important questions:
1) How do the 1-Wire slave devices know they are supposed to be reading or writing?
2) What happens if more than one device is on the bus, trying to write data?

The answer to 1) has to do with the fact that 1-Wire devices have circuitry built into them that monitors time and implements the 1-Wire bus protocol. In effect, each device is independently keeping track of what’s going on. When the master issues a reset, all devices are put into a known state and from that point on they follow a strict, predefined protocol that keeps everybody on the same page in terms of who is supposed to be talking and who is supposed to be listening. With respect to question 2) there are cases when more than one device puts data on the bus at the same time.

This generally occurs when the master is trying to find out what devices are on the bus. During that phase, the master hasn’t had the opportunity to select an individual device, so all are talking at once. Since all the devices on the bus are open collector, with a pull-up, the result is a “wired AND” of the data of all the devices that are trying to talk. The 1-Wire bus protocol specifies the algorithms that allow the master to iteratively, through a process of elimination, identify all the devices on the bus, even in an environment where more than one device is talking at once.

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